STOP_MASTER Assertion during Data Burst
If STOP_MASTER is held asserted, the core will start a DMA cycle and terminate after one word has been transferred.
Figure 6-42 shows a DMA cycle being terminated by STOP_MASTER and a subsequent DMA cycle transferring a
single word. To prevent the DMA cycle in Figure 6-42 from starting, the RD_BUSY_MASTER and
WR_BUSY_MASTER inputs can be used.
cycle
A0 A1 A2 A3
0
1
2
3
4
5
6 A1 A2 A3
0
1
2
3
4
5
clk
framen
cben[3:0]
7
0
7
0
ad[31:0]
ADDR
0
1
ADDR
2
par
devseln
irdyn
trdyn
reqn
gntn
mast_active
stop_master
rd_busy_master
dp_start
dp_done
bar_select[2:0]
0
7
0
rd_cyc
rd_stb_in
rd_stb_out
mem_add[11:0]
000 004
008
00C
mem_data_in[31:0]
0
1
2
3
rd_sync
Figure 6-42 · STOP_MASTER Held Asserted during DMA Burst Read
v4.0
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